Abstract:A VHDL-SPICE mixed-signal modeling methodology is applied to the RF interface of a DECT ASIC designed in CMOS 0.35 f.lm technology. An overview of actual mixed design flows is presented followed by the DECT system description. Then a mixed-signal methodology is introduced to validate the whole circuit behavior. We illustrate the approach with detailed models, simulation results and experimental data. The chip was successfully tested and produced by VLSI Technology.