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served as a consultant and contributed encouragement as well as advice. Dr. J. M. Kopper reviewed the manuscript. Mr. H. W. Snyder constructed the experimental equipment and helped to gather the experimental data. Miss P. M. Powers and Mr. W. A. Ray programmed the digital computers. Mrs. M. D. Denburg and Miss P. A. Shipley performed some numerical calculations and plotted the curves. Mr. C. M.

Inductive noise limits the physical design of high‐speed, high pin‐out chip packages. This paper presents the derivation of some basic equations that are useful for computing inductive noise of various chip packages, and also presents simple asymptotic and limiting results that reduce to some useful approximate results proposed by others. These results are helpful for computing inductive noise in arrays of wire bonds, solder balls, dual in‐line package leads, package pins, and connector pins. Computed results agreed well with measured results. We present two simple rules for minimizing inductive noise and also discuss the inductive noise of power and ground planes.

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