In this paper, we concentrate on the identification of skin cancer. The skin images are taken from a medical database which is a pre-processed image, which is given as input for different machine learning algorithm. The algorithm used is KNN classifier, SVM classifier, and CNN model. where these classifiers will classify whether a given image is cancerous or non-cancerous image. In case of the KNN and SVM the output is 80%, hence in CNN model substantial improvement in accuracy of cancer detection is obtained & it can classify the cancerous & Non-cancerous images efficiently. The process was conducted for test data, training data and validation data using different-images. The training dataset was trained with 100 epochs. The process obtained the accuracy of 97% in training result. in testing result obtained is 95% of accuracy and 96% for validation testing.

Memory systems in many applications are becoming increasingly large, contributing to many challenges in the memory management that has led to many method to manage memory. The tag comparison consumes large amount of cache energy. Current methods provide tag comparison cache or failure of the expected cache. Here is proposed an idea based on new call Comparing Tag stages, filter bloom is presented to improve the efficiency of the cache to predict failure and partial tag comparison for the cold line of verification and full comparison check for direct labels. Moreover, the administration of the cache that is filled with cache lines occurs when there is a cache miss. Today's embedded applications use MPSoC. The  MPSoC consists of the following ie more than one  processors, shared memory among the processors available and a global  off-chip memory. Planning of the activities of an integrated application processor and memory partition between processors are two main critical problem. Here, for an integrated application, both task scheduling and partitioning the integrated available L2 cache to reduce the runtime approach is used.

We describe an optimization for binary radix-16 (modified) Booth recoded multipliers to reduce the maximum height of the partial product array of columns to _n/4_ for n = 64-bit unsigned operands. This is contrast to the conventional maximum height of (n + 1)/4. Therefore, a reduction of one unit in the maximum height of partial product is achieved. The reduction may add flexibility during the design of the pipelined multiplier to meet the required design goals, it may allow further optimizations of the partial product array reduction stage in the area/delay/power and/or may allow additional addends to be included in the partial product array without increasing the delay. The method that can be extended to the Booth recoded multipliers, signed multipliers, combined signed/unsigned multipliers, and other values of n.