This paper describes a new LSI chip set developed to provide a simple and cost-effective means for DSP hardware implementation. This chip set, consisting of two NMOS LSIs, contains enough logic and memOry to perform such high level DSP functions as biquad lilters and FFT buttef lies at a high throughput rate, without any other external logic devices. It employs serial arithmetic and operates at a clock rate up to mote than 5 MHz, Throughput rate can be traded-off with processing accuracy. Architecture is designed to pursue self-sufficient applicability to high level DSP functions, while retaining generalit' in application.

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Abstracr-Two new digital transmultiplexers intended for commercial use have been developed. One transmultiplexer performs a bilateral conversion between two 12-channel FDM'group signals and a 24-channel PCM carrier signal. The other mutually connects two 60channel FDM sllpergroup signals and five 24-channel or four 30channel PCM signals. Both exploit a block processing digital SSB-FDM multiplex/demultiplex scheme employing a cascade of an FFT processor and a set of complex coefficient digital fhters. They have been built using newly developed high-level DSP LSI chips. Algorithmic considerations, developed LSI architecture, and equipment configuration ape described as well as digital processor design details and measured performance.