A newly developed storage dielectric was found to have exceptional competence to prolong the life span of existent NO-based dielectrics by adopting N 2 O wet oxidation and postoxidation treatment. Compared with the conventional NO dielectric, 12.6% cell capacitance enhancement can be achieved while keeping a comparable leakage current. The reliability performance is also qualified with less than 438 ppm failure rate after 10-years of operation. In addition to the distinguished electrical characteristics, the intriguing point is its process simplicity since the N 2 O-related process could be fully integrated into the current furnace process. Combining the promising properties, this economical technique would be favorable for dynamic random access memory ͑DRAM͒ manufacturers to control their chip cost in the increasingly competitive arena.The 1 transistor-1 capacitor ͑1T-1C͒ based dynamic random access memory ͑DRAM͒ has long predominanted in the high-density memory arena for past decades and is the ubiquitous workhorse in almost all personal computers ͑PC͒ currently in use. As process technology aggressively scales into 110 nm regime and beyond, it has been found more and more difficult to meet the reliability and speed requirements. One of the major reliability requirements is driven by the need to maintain storage capacitance despite continuous reduction in bit storage area. For trench DRAM, besides some well-established capacitor surface area enhancement techniques which encompass hemispherical grains ͑HSG͒ 1-4 and bottle-shaped deep trenches, 2-4 high-k materials such as Al 2 O 3 1,2,4 and HfSiO 5 serving as the storage dielectric have been extensively discussed and successfully integrated into trench technology. High-k material is assuredly the inevitable trend for DRAM, radio frequency ͑rf͒ mixed signal integrated circuit ͑IC͒ 6,7 and complementary metal oxide semiconductor ͑CMOS͒ 8,9 development. However, trench DRAM chipmakers will spend more on capital expenditures on advanced equipment such as atomic layer deposition ͑ALD͒ tool 4,5 for high-k process at their 300 mm plants because of cost considerations. Under the circumstance, for 200 mm plants, it becomes imperitive to explore the possibility for extending the use of incumbent nitride/ oxide ͑NO͒ storage dielectric for the next generations. In our previous work, 10 NO storage dielectric founds its extensibility by transforming the oxide layer into oxynitride through additional nitridation and reoxidation. Enhanced cell capacitance with satisfactory leakage current and reliability are exhibited via this scheme. This approach, however, achieves such promising electrical characteristics at the price of adding extra cost because the additional nitridation and reoxidation are conducted under low pressure conditions, much different from the growth condition of oxide layer which is in atmosphere. This means an additional furnace process and consequent expenses are inevitable. In this work, in situ nitrous oxide ͑N 2 O͒ wet oxidation is proposed to circumvent t...

Si nanocrystal with a high density of 5.1 ϫ 10 11 cm −2 and an average size of 7.2 nm has been achieved on the NH 3 -nitrided tunnel oxide, and the density is higher than that formed on the untreated tunnel oxide by a factor of 3.2. The higher density obtained by this technique is attributed to the lower activation energy for the Si nanocrystal nucleation growth on the nitrogen-containing surface of the nitrided tunnel oxide. The memory device with such a high nanocrystal density demonstrates a 1.79 V threshold voltage shift by programming at 10 V for 10 ms and a negligible memory window degradation up to 10 6 program/erase cycles. The good charge storage capability is evidenced by an extrapolated 10 year memory window of 0.92 V at 150°C.Because of the widespread adoption in consumer electronics and the growing demand in personal computer applications for nonvolatile memory, it has drawn intensive research interest in further scaling the memory cell size and reducing the operation voltage of the current floating-gate-based nonvolatile memory. With the mutually isolated and discrete charge trapping sites, nanocrystal memory has been regarded as one of the most promising flash memory technologies due to its better scalability, lower program/erase voltage, and enhanced endurance performance. In addition, compared with polycrystalline Si-oxide-nitride-oxide-Si ͑SONOS͒, the other widely investigated charge-trapping memory, it reveals several merits in more controllable trap sites and larger trapping probability. 1 Owing to the fully compatible process of incumbent ultralarge-scale integration technology, Si nanocrystal memory has received much attention for years. 2-12 Nevertheless, Si nanocrystal memory still exhibits a limited retention and a small memory window that would restrict its potential application for nonvolatile memory. To address this issue, many research groups have proposed structures including highpermittivity interpoly dielectric, 2 highly field-sensitive nitrideoxide-nitride as the tunnel barrier, 3 doubly stacked Si nanocrystal, 4 surface-nitrided Si nanocrystal, 5 and hybrid Si nanocrystal Si nitride memory. 6 However, few reports discuss the approach to form highdensity Si nanocrystal, which is essential to further boost the program/erase speed and memory window. Si nanocrystal fabricated by ion implantation of excess Si into the oxide and subsequent thermal annealing is a straightforward method to control the nanocrystal density; 7 unfortunately, it would compromise the tunnel oxide quality. Although high-density Si nanocrystal formed by low-energy SiH 4 plasma immersion ion implantation seems to be practically feasible, 8 it necessitates a different type of ion implantation tool to implement. In this article, with the existent standard process tools in a mass production fabrication, high-density Si nanocrystal formation has been achieved on the appropriately nitrided tunnel oxide. The large memory window with a good endurance performance from the electrical characterization of the memory device...

Abstract-A simplified and integrated technique has been proposed to form an oxide/nitride storage dielectric in a single-furnace process by low-pressure oxidation and nitride film deposition with an extra N 2 O treatment for the trench dynamic random access memory (DRAM). Compared to the conventional nitride/oxide dielectric, this newly developed dielectric enjoys cellcapacitance-enhancement factor as high as 12.5% without degrading the leakage current and electron-trapping property. From the reliability test, the qualification for the DRAM application is also proven by the dielectric lifetime longer than 10-years. Most importantly, this technique can reduce the production cycle time without an additional equipment investment, which is essential in the cost-competitive DRAM arena.Index Terms-N 2 O treatment, oxide/nitride (ON) stack, singlefurnace process, storage dielectric, trench dynamic random access memory (DRAM).

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