A static condenser is an advanced Static VAR Compensator (SVC) using voltage source converters with capacitor connected on the DC side. It has several advantages over both rotating synchronous condensers and variable impedance type SVCs and is expected to make a major breakthrough in the reactive power control in electric utility systems. This paper presents the mathematical modelling and asalysis of static condenser. The control parameters are based on eigenvalue analysis and the performance evaluated from digital simulation. The results from a case study show the benefits of static condenser in improving system stability and thereby increasing the power transfer in the line.

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A Field Programmable Gate Array (FPGA) based hardware accelerator for multi-conductor parasitic capacitance extraction, using Method of Moments (MoM), is presented in this paper. Due to the prohibitive cost of solving a dense algebraic system formed by MoM, linear complexity fast solver algorithms have been developed in the past to expedite the matrix-vector product computation in a Krylov sub-space based iterative solver framework. However, as the number of conductors in a system increases leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products present a time bottleneck, especially for ill-conditioned system matrices. In this work, an FPGA based hardware implementation is proposed to parallelize the iterative matrix solution for multiple RHS vectors in a lowrank compression based fast solver scheme. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple conductors in a Ball Grid Array (BGA) package. Speed-ups up to 13x over equivalent software implementation on an Intel Core i5 processor for dense matrix-vector products and 12x for QR compressed matrix-vector products is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board.

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