No abstract

No abstract

Universal Verification Methodology (UVM) caters to an essential role in verifying the different categories of circuits ranging from small-scale chips to complex system-on-chip architectures. Constrained random simulations are an indispensable part of UVM and are often used for design verification. However, the effort and time spent manually updating and analyzing the design input constraints result in high time complexity, which typically impacts the coverage goal and fault verification ratio. To overcome this problem, this paper proposes a novel hybrid optimized verification framework that combines Reinforcement Learning (RL) and Deep Neural Networks (DNN) for automatically optimizing the input constraints, accelerating faster verification with a high coverage ratio. The proposed algorithm uses reinforcement learning to generate all possible vector sequences needed for testing the target devices and corresponding outputs of the target devices and potential design errors. Furthermore, the framework intends to use high-speed deep-feedforward neural networks to automate and optimize the constraints during runtime. The proposed framework was developed using Python interfaced with the TCL environment. Extensive experimentation was carried out using several circuits, including multi-core designs, and performance parameters such as coverage accuracy, speed, and computational complexity were calculated and analyzed. The experiment demonstrated the proposed framework remarkable results, showing its superior performance in faster coverage and fewer misclassification errors. Furthermore, the proposed framework is compared with existing verification frameworks and other classical learning models. Good results demonstrate that the proposed framework increases the 4.5x speed for verifying multi-core designs and the 99% accuracy of detection and coverage.