A new approach is suggested to approximate the amplitude frequency behaviour of a given high Q poles network function, by an explicit function having poles with a predetermined desired low Q, and with explicit knowledge and control of the error. The method is practical for reducing Q's by the ratio of up to 6. Any critical pole-pair is replaced by an approximating function possessing a complex conjugate n-th order pole-pair and a ( n -1)-th order zero-pair. A general second order low Q building block is derived as an example. Measured results proving the practical usefulness of the method, are reported.

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The DesignThis paper presents a novel clock distribution scheme to achieve low skew in high-speed VLSI systems. The method was devised to solve the problem of distributing a 1 .O GHz clock along a 1 .O Gbps 10-channel wide PECL to CMOS interface circuit. The differential clock signals are distributed along a lossy transmission line which is connected between the differential input stage of an amplifier and the diode-connected load of the differential amplifier, forming a distributed differential amplifier which is in effect the clock distribution circuitry. This scheme results in a simulated skew of less than 20.0~s across 3600 pm. Although the targeted clock frequency is very close to the performance limits of the technology, our approach increases the operating frequency of practical VLSI systems in 0.8 pm CMOS technology.

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