No abstract

This paper presents a comprehensive investigation of statistical effects in deeply scaled nitride memory cells, considering both atomistic substrate doping and the discrete and localized nature of stored charge in the nitride layer. By means of 3-D TCAD simulations, the statistical dispersion of the threshold voltage shift induced by a single localized electron in the nitride is evaluated in presence of non-uniform substrate conduction. The role of 3-D electrostatics and atomistic doping on the results is highlighted, showing the latter as the major spread source. The threshold voltage shift induced by more than one electron in the nitride is then analyzed, showing that for increasing numbers of stored electrons a correlation among single-electron shifts clearly appears. The scaling trend and the practical impact of these statistical effects on cell operation are discussed in Part II of this paper.

We present a detailed semi-analytical investigation of the transient dynamics of gate-all-around (GAA) chargetrap memories. To this aim, the Poisson equation is solved in cylindrical coordinates, and a modification of the well-known Fowler-Nordheim formula is proposed for tunneling through cylindrical dielectric layers. Analytical results are validated by experimental data on devices with different gate stack compositions, considering a quite extended range of gate biases and times. Finally, the model is used for a parametric analysis of the GAA cell, highlighting the effect of device curvature on both program/erase and retention. Index Terms-Charge-trap (CT) memories, Fowler-Nordheim (FN) tunneling, gate-all-around (GAA) memories, semiconductor device modeling.

We present a new physics-based model able to reproduce the program/erase transients in TANOS memories, accurately describing the charge trapping/detrapping dynamics in the nitride layer. Modeling results are extensively validated against a large number of experimental data taken on samples with different gate stack compositions, considering a quite extended range of program/erase voltages and times. The good agreement between experimental and simulated results makes the developed model a useful tool for the assessment of the performance achievable by the TANOS technology.

This paper presents a physics-based model that is able to describe the TANOS memory programming transients in the Fowler-Nordheim uniform tunneling regime across the bottom-oxide layer. The model carefully takes into consideration the trapping/detrapping processes in the nitride, the limited number of traps available for charge storage, and their spatial and energetic distribution. Results are in good agreement with experimental data on TANOS devices with different gate-stack compositions, considering a quite extended range of gate biases and times. The reduced gate-bias sensitivity of the programming transients with respect to the floating-gate cell is explained in terms of a finite number of nitride traps and a thinner extension of the nitride trapping region as the gate bias is increased. The model represents a valid contribution for the investigation of the achievable performances of the TANOS technology.