No abstract

In today's highly competitive semiconductor IC market, it is critical to address the market requirements of low cost, superb performance, and high reliability for the success of any product. It becomes increasingly challenging to meet these requirements that sometimes conflict with each other. Skyworks recently developed a third generation pseudomorphic high electron mobility transistor (PHEMT) process with reduced gate pitch and ohmic width geometry to increase the FET density factor. While this initiative significantly improves the throughput, we have launched a series of reliability experiments to assess the possible impacts on device reliability. Potential issues include greater leakage, smaller breakdown voltage, and hotter channel under the same electrical bias conditions.The objectives of this work are to: (1) Reduce chip size for improved throughput per wafer and more cost competitive products; (2) Evaluate the electrical performance and reliability of this third generation PHEMT process (PH3) in comparison with standard second generation (PH2) baseline process; (3) Ensure that the long-term reliability is not compromised for throughput; (4) Feedback the results to process engineering and management for continuous improvement and process release.Test vehicles are 0.5-pm gate etch-stop PHEMTs with both single-gate and triple-gate transistors from thee lots and ten wafers. The width of each finger is 230 pm, and the selected PCM (process control monitor) structures contain two fingers in each FET for both single-gate and triple-gate devices, giving a total width periphery of 460 pm. Experiments include:1. Two sets of step stress tests: (a) constant Ids = 34.5 mA with stepping vds from 3-12 V while maintaining constant channel temperature Tch = 250°C by adjusting ambient temperature T,; (b) constant electrical stress at 6 V x 34.5 mA = 207 mW with stepping T, from 160-240°C. Each experiment has 15 samples and the duration in each stress step was 15 hours. These tests allow a quick assessment of the possible failure modes and provide useful reference information for designing long-term stress tests. 2. Single temperature 1000-hour qualification test with 45 samples stressed at 4 V x 34.5 mA = 138 mW, and T, = 200°C or Tc,,= 238°C.3. On-wafer-level highly accelerated step stress with electrical power stress from 300 to 700 mW, giving Tch= 286-410°C. 4. Four-temperature constant high-temperature operating life (HTOL) stress with Tch = 21 7-279OC over 3,500 hours. 5. Side-by-side comparison test on both PH3 and PH2 processes. Stress conditions include on-state as well as off-state electrical biases 011 both processes. This paper will focus on description of the last three experiments listed above.