High-efficiency video coding (HEVC) is based on integer discrete cosine transforms (DCTs) of size 4 × 4, 8 × 8, 16 × 16 and 32 × 32 whose elements are coded on 8 bits. However, the algorithm requires that the output length at each processing stage should never exceed 16 bits. The conventional solution is the truncation of the least significant bits which leads to erroneous results and a waste of resources. In this Letter, different DCT kernels with reduced elements length are proposed. They are evaluated for compression efficiency and hardware implementation competence. An implementation on the Xilinx FPGA virtex-6 circuit has given a maximal operating frequency increase of 4.81 and 93.41% for the DCT-II 4 × 4 and the discrete sine transform, while reducing the energy consumption by 10.64 and 30.77% at 100 MHz, respectively. Using the HM 16.3 HEVC model and video sequences of different resolutions, the results show a quality degradation of 0.01 dB for a bit rate increase of 0.19% compared to the reference cores.

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