Multilevel converters are being considered for an increasing number of applications due to their high power capability, associated with lower output harmonics and lower commutation losses. Their main disadvantage is their complexity which requires both a great number of power devices an a rather complex control circutry. In this work a new inverter topology using an auxiliary switch is presented, reducing the number of power devices required to implement a multilevel output. The topology is tested in the design of a 5 levels H bridge simplified inverter; circuit operation is presented, simulated in SPICE and validated with experimental tests performed on a laboratory prototype. Additionally, the dedicated modulator circuit required for multilevel inverter operation is implemented using a FPGA circuit, reducing overall system cost and complexity.

Abstract. In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic timing simulation. This model is called Delay Degradation Model (DDM). Characterizing DDM completely also implies the characterization of the normal propagation delay. In this paper, we propose a simple heuristic model that includes its dependence on the output load and the input transition time. We have tested this model and found a mean deviation lower than 4%. Also, we present a characterization process for this model that is fully integrated into AUTODDM without affecting the total simulation time needed to characterize a standard cell.

Abstract-Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementation is presented, allowing for full hardware implementation of synchronization systems. Measurements on field-programmable gate array prototypes show a fast convergence time (below 10 s) and a high accuracy (1 µs) for typical configuration parameters.