An ultralow-standby-power technology has been developed in both 0.18-m and 0.13-m lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage sixtransistor (6T) SRAM cell sizes are 4.81 m 2 and 2.34 m 2 , corresponding respectively to the 0.18-m and 0.13-m design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25ЊC and is less than 400 fA per cell at 1.5 V, 85ЊC. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the wellknown gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

In this paper, we compare the distortion and power characteristics between AlGaN/GaN high-electron-mobility transistors (HEMTs) with different epi-structures. Third-order intermodulation distortion (IM3) measurement evaluates distortion characteristics, and on-wafer load and source-pull measurements evaluate the power performance. The results show that the AlGaN/GaN HEMTs directly fabricated on GaN substrates without nucleation layer perform better than those fabricated on SiC substrates. Furthermore, the distortion performance is compared with and without field plate.