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A comparison between the Wiener least square solution and the LMS algorithm in the FIR digital filter synthesis by adaptive modeling is presented. In the LMS case, a "cut and try" technique is less appropriate because changes in the weights of the cost function affect the desired frequency points as well as the frequency points where a good approximation of the frequency response was already obtained.

A real-time adaptive self-tuning digital filter has been implemented for audio-band using the TMS320C30. An 81-tap finite impulse response (FIR) filte was utilized. Attempts to optimize the filter performance produced a signal-to-noise ratio improvement of 13db., a misadjustment noise reductioin by a factor of 50% from a U = 0.01 to a U = 0.001 while yielding adaptation speed degradation by a factor of 8

The Motorola DSP56000 and the Texas Instruments TMS3uwyL5 digital signal processors have been used to implement real-time finite impulse response (FIR) filters. Calculations were made to predict the number of instruction cycles needed to implement the FIR kernels of the assembly language programs, and the complete programs including inputloutput routines. Calculations based on the manufacturers published data on instruction execution speeds showed that the FIR kernel of the DSP.56000 assembly language program for an n-tap FIR would execute in (n+3) instruction cycles, whereas that of the TMS32OC25 would execute in (n+7) instruction cycles. The calculations also predicted that, at a sampling rate of 48 KHz, the DSP56000 and the TMS320C25 would be able to implement up to 194-tap and 192-tap FIR filters respectively. At 40 KHz sampling rate. a maximum of 234-tap FIR filter was calculated for the TMS320C25, and an experimental value of 227 was realized. For a sampling rate of 48 KHz, a maximum of 194-tap FIR filter was calculated for the DSP56000 and an experimental value of 200 was realized. For a processor clock speed of 40 MHz, the instruction cycle time of the TMS32OC25 is 100 ns. At a processor clock speed of 20.45 MHz, the instruction cycle time of the DSPSMXX) is 97.5 ns.

The execution speed of the Motorola DSP96002 is assessed, by establishing the maximum number of taps of FIR filters that can be implemented in real time. Calculations using manufacturer supplied data yielded a theoretical value of 324 for maximum number of taps for real-time FIR-. Real time measurements produced results of 325 for the maximum number of taps. This translates to the execution of an FIR kernel in (2N+24) clock cycles. The 96002 was run at 33.3MHz, and the sampling rate was 48KHz. Establishing such throughput limitations is crucial in time critical applications.Introduction: