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II. ARCHITECTURE OVERVIEW AND INSTRUCTION SET The ST18940 is the third member of the SGS-THOMSON Microelectronics ST1 8 digital signal processor family. The use of an advanced CMOS The extended harvard architecture of the DSP is technology (1 .2 micron) combined with a highly designed around a 32-bit wide instruction bus and cessing algorithms. To a wide range of appli-internal memories or I/O interfaces and the data arithmetic unit. The third data bus (Z bus) allows the cations, twoversions are provided : aclosed version with on-chip masked program ROM and an open transfer of calculation results into the internal or version, which can 64 words of external external memories and all possible move from register to register. There are four types of microprogram memory. instruction : data processing with move, data move, parallel architecture provides a powerful and efficient DSP as demonstrated on usual signal pro-three data buses (L and R, carry the Operands between &bit data buses as shown On figure '' branch and literal load. ~ One key feature of the ST 18940/41 is its capability I WCAL 24%