Current system-on-chip implementations integrate IP blocks from different vendors. Typical problems are incompatibility and integration overheads. This paper presents a case study of integrating two black-box hardware accelerators into highly scalable and modular multiprocessor system-on-chip architecture. The integration was implemented by creating two wrapper components that adapt the interfaces of the hardware accelerators for the used architecture and on-chip network. The benefit of the accelerators was measured in three different configurations and especially the execution time overheads caused by the software, data delivery, and shared resource contention were extracted and analyzed in MPEG-4 encoder. The overheads increase the function runtime up to 20x compared to the ideal acceleration. In addition, the accelerator that seemed to be more efficient performed worse in practice. As a conclusion, it is pointed out that the integration induces great overhead to the execution time, rendering a-few-clock-cycle optimizations within the accelerator meaningless.

This paper presents a new method for run-time management of shared processing resources in multiprocessor systems on chip. A centralized resource manager unit performs dynamic allocation of shared processing resources according to the system state and given constraints. It implements a hardware mutual exclusion so that no inter-processor synchronization is required for accessing the resources. Moreover, it supports dynamic power management. In addition, a hardware implementation of the resource manager is proposed. In a case study, a resource manager is evaluated in a data-parallel MPEG-4 video encoder on multiprocessor system on chip on FPGA. The RM eases the design of six different architectures featuring two to twelve shared hardware accelerators. Only a few accelerators are required for the best performance as the accesses are efficiently scheduled.