In this paper, silicon npn bipolar transistors with indium-implanted base regions are discussed. Polysilicon emitter bipolar transistors are fabricated using a standard 0.5-m BIC-MOS process flow [1] where the base BF2 implant is replaced by an indium implant. In indium-implanted transistors, the integrated hole concentration (G b ) in the quasi-neutral base is reduced due to incomplete ionization of indium acceptor states. The novel utilization of this impurity freeze-out effect results in much increased collector currents and common-emitter transistor gains (h fe ) compared to boron-implanted transistors. Also, since indium acceptor states in depletion regions become fully ionized, the spreading of the reverse-biased collector-base junction depletion region into the transistor base (base-width modulation) is minimized. Hence, for indium base bipolar transistor an improved h fe -V A product is anticipated. Our first attempt at fabricating bipolar transistors with indium-implanted base regions resulted in devices with greatly increased collector current, impressive gains of h fe 1600, excellent collector current saturation characteristics, an Early Voltage of V A 10 V, h fe -V A product of 16 000 (implying an extended device design space), base-emitter breakdown voltages of BV EBO 9:6 V, and a cut-off frequency of ft = 17:8 GHz.

A 0.25-pm modular High-Engery Implanted BiCMOS (HEIBiC) technology has been developed for high-integration wireless-communication systems. It integrates an RF bipolar transistor into CMOS process [ l ] without disturbing CMOS device characteristics. HEIBiC technology utilizes implantation to form the base, collector and CMOS tubs. This single-poly emitter npn transistor demonstrates an fT=52 GHz for 2.5 V devices and an fTBVCEo product of 171 GHz-V for 3.3 V devices. The performance of HEIBiC technology is competitive with the best reported in the literature.