It is well known that dc offsets degrade the performance of analog adaptive filters. In this paper, the effects of dc offsets on four variations of the stochastic gradient algorithm are analyzed. Assuming a Gaussian probability distribution for the input signal and error signal, the output mean squared error (MSE) performance in the presence of dc offsets is evaluated for each of the algorithms. The theoretical work is compared with computer simulations and the results, together with convergence properties of each of the algorithms and their respective hardware requirements, are used in selecting the most appropriate algorithm. Although a Gaussian input distribution is assumed, it may reasonably be inferred that the critical results obtained should also hold for other input distributions.

A balanced transconductance-C biquad implemented in the digital subset of a 0.9-um CMOS process operates at frequencies up to 450 MHz and Q factors from a nominal value near 1 to approximately 100 with 30-40-dB dynamic range. By switching in capacitors and adjusting control voltages it can be tuned to below 30 MHz, demonstrating the capability of operating over the entire VHF range. Active area is 0.029 mm2 and power consumption is 8-12 mW with a 5-V power supply.

A 125Mbaud quad transceiver for lO/lOO fast ethernet has been designed in a 5V 0.35pm digital CMOS process. Power consumption for the device is 3W. Detailed testing show excellent receiver results with error free performance up to 160m under worst-case baseline wander and crosstalk conditions. The analog receiver uses digital adaptation circuitry to optimize an automatic gain control circuit with baseline wander correction, an equalizer and a DC offset correction circuit.

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