We address the issues of throughput, security and interference in wireless LANs by proposing a multi-channel, wideband approach to access points that requires no change to client silicon. Our solution integrates three fully asynchronous 802.11a/b/g-compliant modems with a wideband spectrum monitor.

The principle organization of memory elements to store data that perform two dimensional transpose applications is presented. The memory element is designed using Mentor graphics software. This memory unit is utilized in the design of two-dimensional median filter. The VHDL code used in the implementation of Median filters is detailed. The overall design and its outcomes are described.The storage inverters drive a buffer inverter N4 and P4 which in turn drives two read lines through pass transistors N5 and N6. Additional read ports are constructed by adding transistors at the output of inverter N4 and P4 and adding additional read-row decode lines. Additional write lines are added by adding transistor that drive inverters N2 and P2 and N3 and P3. A benefit of this design is that no matter what load appears on the output of the buffer inverter, the state of the memory cell cannot be flipped. I. Introduction 11. VHDL Implementation On-chip memory can be designed for high speed and unique access paths. Register files are generally fast IMMs with multiple read and write ports. Conventional RAM cells may be made multi-ported by adding pass transistors[l] as shown in the figure 1. This is a single-write, double-read-port cell. The write port is a single-ended implementation wherfe the write pass transistor N1 is used to over-drive a weak feedback inverter N3 and P3. The threshold of storage inverter N2 and P2 is biased towards Vss by increasing the size of N2 with respect to P2 to aid in the writing of the cell. wrike data Fig. 1. Multi-ported RAM cells 0-7803-5491-5/99/$10.00 0 1999 E E E read-r,eaddata0 d.atal 732The control of this register file is handled by the address (Ad), a read (Rd) command, and a write (Wr) command. All these signals are synchronized on a clock (Ck). Register file data are read or written throilgh the bidirectional bus Data. A VHDL description of the register file is shown in figure 3. The external view of the register file is shown in figure 2. Fig. 2. External View of the Register FileThe control of this register file is handled by the address (Ad), a read (Rd) command, and a write (Wr) command, All these signals are synchronized on a clock (Clk). Register file data are read or written through the bidirectional bus Data. A VHDL[2] description of the register file is described below: LIBRARY ieee; USE ieee.std-logic-1164.ALL; USE ieee..numeric-std.ALL; ENTITY memory IS PORT(C:lk : IN std-ulogic; lid : IN std-ulogic; 'Nd : IN std-ulogic; Ad Data : INOUT Std-logic-vector : IN unsigned(5 DOWNTO 0);

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