Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture.The SCalable ARChitecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures; tools for synthesizing architectures from application or application-area; VLSI cell libraries and tools for quick generation of application-specific processors; a system-software platform which can be retargeted quickly to fit the applicationspecific architecture;This paper concentrafw primarily on the architecture framework of SCARCE, but RIW presents briefly some software issues and outlines the process of generating VLSI processors.

The SCARCE architecture framework allows the costeffective design of application-specific architectures for a wide variety of embedded applications (controllers, signal processing, graphics). Costeffective in this context means reduction of recurrent hardware and software development costs while achievTo aid efficient control over the design and documentation process we have integrated the framework in the ASA silicon compilcr from Sagantec Inc.. The SCARCE fiamework is completely described by means of the Sagantec hardware description language, SID. Generating an application-specific processor reduces to a number of SID-description transformations. Currently these transformations are by hand, in the future all transformations will be made automatically.Generating the processor layout from the SID description is &ne by the ASA silicon compiler. To optimize the resulting layout, custom building blocks are being integrated as regular structures.Since all descriptions are in SID. the ASA silicon compiler allows simulation to take place on all stages of processor development.In this paper we describe the overall structure of the SCARCE framework, its representation in the SID description language, and the processor design trajectory.ing high performance.