The effects of bias stress on transistor performance are important when considering nontraditional channel materials for thin film transistors. Applying a gate bias stress to indium gallium zinc oxide transparent thin film transistors was found to induce a parallel threshold voltage shift without changing the field effect mobility or the subthreshold gate voltage swing. The threshold voltage change is logarithmically dependent on the duration of the bias stress implying a charge tunneling mechanism resulting in trapped negative charge screening the applied gate voltage.

Indium gallium zinc oxide deposited by pulsed laser deposition at room temperature was used as a channel layer to fabricate transparent thin film transistors with good electrical characteristics: field effect mobility of 11cm2V−1s−1 and subthreshold voltage swing of 0.20V∕decade. By varying the oxygen partial pressure during deposition the conductivity of the channel was controlled to give a low off-current of ∼10pA and a drain current on/off ratio of ∼5×107. Changing the channel layer thickness was a viable way to vary the threshold voltage. The effect of the gate dielectric on the electrical behavior was also explored.

In pure zirconia, ultrafine powders are often observed to take on the high‐temperature tetragonal phase instead of the “equilibrium” monoclinic phase. The present experiments and analysis show that this observation is one manifestation of a much more general phenomenon in which phase transformation temperatures shift with crystallite/grain size. In the present study, the effect of crystallite (for powders) and grain (for solids) size on the tetragonal → monoclinic phase transformation is examined more broadly across the yttria–zirconia system. Using dilatometry and high‐temperature differential scanning calorimetry on zirconia samples with varying crystallite/grain sizes and yttria content, we are able to show that the tetragonal → monoclinic phase transformation temperature varies linearly with inverse crystallite/grain size. This experimental behavior is consistent with thermodynamic predictions that incorporate a surface energy difference term in the calculation of free‐energy equilibrium between two phases.

A transparent memory device has been developed based on an indium gallium zinc oxide thin film transistor by incorporating platinum nanoparticles in the gate dielectric stack as the charge storage medium. The transfer characteristics of the device show a large clockwise hysteresis due to electron trapping and are attributed to the platinum nanoparticles. Effect of the gate bias stress (program voltage) magnitude, duration, and polarity on the memory window characteristics has been studied. Charge retention measurements were carried out and a loss of less than 25% of the trapped elec-trons was observed over 104 s indicating promising application as nonvolatile memory.

No abstract