As the technology is scaling downs day by day designing of radio frequency integrated circuit (RFIC's) is introduces more challenges in the world of electronics. The challenges are such as area gain, size, and leakage current, electrostatic discharge (ESD), power consumptions & so many, raises the threat while designing the electronic circuitry. Among all these challenges we are focusing on the ESD-protection because of 70% of IC's are fails due to ESD happening. Reliability of IC's is one of the most important factor semiconductor industries. SD protection of RFIC is very challenging job due to lack of various ESD models & their proper communication with core circuit. Here a novel co-design methodology is suggested which is a simulation based process. In this technique a 130nm or 0.13μm CMOS technology is used & for ESD protection LVTSCR (Low Voltage Triggered Silicon Controlled Rectifier) is incorporated. The extracted results are compared. Such as without ESD protection (core circuit) & with ESD protection circuit (Protection +Core Circuit).The RF-ESDdesign of 5GHz to 6GHz LNA is used to show the implementation of this novel technique. A novel co-designed ESD protected LNA circuit achieves good on chip performance, including 4-kV ESD protection, a gain of 16.770 dB, noise figure 3.025 dB, input matching -8.454 dB, and output matching is -12.233 dB in same LNA-ESD protected design.