We study magnetization reversal and first order reversal curves for two different magnetic topological semimetals, Co3Sn2S2 and Fe3GeTe2, in a wide temperature range between 80 K and 180 K. For the magnetization hysteresis loops, we observe strong temperature dependence of the initial (low-temperature) step-like magnetization switchings, so asymmetric regions of slanted magnetization appears above 140 K. Usually, similar behavior is ascribed to appearance of the second, temperature-induced magnetic phase. However, first order reversal curve analysis shows two-phase behavior even at lowest temperatures of our experiment. While the bulk ferromagnetic phase is of high temperature dependence, the second magnetic phase demonstrates perfect temperature stability below the Curie temperature. We connect the robust second phase with the surface spin textures, which are inherent for magnetic topological semimetals, so the excellent temperature stability is due to the topological protection of the semimetal surface states. This conclusion is also supported by the characteristic bow-tie magnetic hysteresis loops.

The concept of a polar metal proposes new approach of current-induced polarization control for ferroelectrics. We fabricate SnSe/WTe2 heterostructure to experimentally investigate charge transport between two ferroelectric van der Waals materials with different polarization directions. WTe2 is a polar metal with out-of-plane ferroelectric polarization, while SnSe ferroelectric semiconductor is polarized in-plane, so one should expect complicated polarization structure at the SnSe/WTe2 interface. We study dI/dV (V ) curves, which demonstrate sharp symmetric drop to zero dI/dV differential conductance at some threshold bias voltages ±Vth, which are nearly symmetric in respect to the bias sign. While the gate electric field is too small to noticeably affect the carrier concentration, the positive and negative threshold positions are sensitive to the gate voltage. Also, SnSe/WTe2 heterostructure shows re-entrant transition to the low-conductive dI/dV = 0 state for abrupt change of the bias voltage even below the threshold values. This behavior can not be observed for single SnSe or WTe2 flakes, so we interpret it as a result of the SnSe/WTe2 interface coupling. In this case, some threshold value of the electric field at the SnSe/WTe2 interface is enough to drive 90◦ change of the initial SnSe in-plane polarization in the overlap region. The polarization mismatch leads to the significant interface resistance contribution, analogously to the scattering of the charge carriers on the domain walls. Thus, we demonstrate polarization state control by electron transport through the SnSe/WTe2 interface.

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We experimentally investigate capacitance response of a thick ferroelectric GeTe single-crystal flake on the Si/SiO2 substrate, where p-doped Si layer serves as a gate electrode. We confirm by resistance measurements, that for three-dimensional flakes, electron concentration is not sensitive to the gate electric field due to the screening by bulk carriers. Unexpectedly, we observe that sample capacitance C is strongly diminishing for both gate field polarities, so C(Vg) is a maximum near the zero gate voltage. Also, we observe well-developed hysteresis with the gate voltage sweep direction for the experimental C(Vg) curves. From our analysis, the capacitance behavior is explained by the known dependence of the Rashba parameter on the electric field for giant Rashba splitting in GeTe. In this case, the hysteresis in capacitance should be ascribed to polarization evolution in GeTe surface layers, which also allows to realize the regime of dynamic negative capacitance. The latter can be directly observed in time-dependent resistive measurements, as non-monotonic evolution of voltage response to the step-like current pulse. Thus, the negative capacitance regime can indeed improve performance and, therefore, the energy efficiency of electronic devices.