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Abstrud-Hopfield's neural networks show retrieval and speed capabilities that make them good candidates for content-addressable memories (CAM's) in problems such as pattern recognition and optimization. This paper presents a new implementation of a VLSI fully interconnected neural network with only two binary memory points per synapse (the connection weights are restricted to three different values: + 1,O and-1). The small area of single synaptic cells (about lo4 pm') allows the implementation of neural networks with more thut 500 neurons. Because of the poor storage capability of Hebb's learning rule, especially in VLSI neural networks where the range of the synapse weights is limited by the number of memory points contained in each connection, a new algorithm is proposed for programming a Hopfield neural network as a high-storage capacity CAM. The results of the VLSI circuit programmed with this new algorithm are very promising for pattern recognition applications. He first joined the Laboratoire Central d'Electricite, Brussels, working in RF1 measurements until 1959. Since then he has been with the

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Neural networks used as content-addressable memories show unequaled retrieval and speed capabilities in problems srreh as vision and pattern recognition. We propose a new implementation of a VLSI fully interconnected neural network with only two binary memory points per synapse. The small area of single synaptic cells allows implementation of neural networks with hundreds of neurons. Classical learning algorithms like the Hebb's rule show a poor storage capacity, especially in VLSI neural networks where the range of the synapse weights is limited by the number of memory points contained in each connectiorq we propose a new algorithm for programming a Hopfield neuraf network as a high-storage content-addressable memory. The storage capacity obtained with this algorithm is very promising for pattern recognition applications.

A new carry-free division algorithm will be described; it is based on the properties of RSD arithmetic to avoid carry propagation and uses the minimum hardware per bit i.e. one full-adder. Its application to a 1024 bits RSA cryptographic chip will be presented. Thanks to the features of this new algorithm, high performance (8 kbits/s for 1024 bits words) was obtained for relatively small area and power consumption (80 mm2 in a 2 pm CMOS process and 500 mW at 25 MHz).