Nowadays, modern embedded applications are becoming more and more complex and resource demanding. Fortunately, Systems on Chip (SoC) are one of the keys used to follow their requirements that stand in need of high performance while maintaining a low-power profile. On one hand, today, due to the limited power budget imposed by the batteries, power is the limiting factor of the logic CMOS. On the other hand, the downscaling of the technology node for 65 nm and beyond, based on the International Technology Roadmap for Semiconductors (ITRS) as a reference, has not only resulted in huge energy consumption but also increased the temperature chip. To address this challenge, designing at the system level is the suitable measure to tackle with the complexity of the Systems on Chip, aiming at having better adjustment between timing and accuracy for power and temperature estimations. We present in this paper, at the first stage, two models describing the static and dynamic power at the physical level. These models are implemented on an open virtual platform Model Power-Consumption and Temperature in SystemC/TLM (LIBTLMPWT) based on a representative SoC architecture. At the second stage, we focus on power, especially the thermal behaviour of the chip while running three benchmarks set on the game of life application for two different technology nodes.

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Simulating systems on a chip (SoC) even before starting its productivity makes it possible to validate the correct functioning of the systems, also avoiding the manufacture of defective chips. However, low-level design and system complexity makes verification and simulation more complicated and time consuming. The classification of the different levels of abstraction from lowest to highest generally depends on the estimation accuracy of the system performance and the speed of simulation. The RTL (Register Transfer Level) abstraction level allows efficient description at gate level with good precision. Therefore, RTL program are slowly simulated. Simulation speed usually depends on the size of the platform used, which is not the case for transaction level modeling (TLM) to achieve simulation speed based on the exchange of transactions between system modules. This work aims to give a detailed description of the different levels of abstraction with the main advantages, and disadvantages on the performances estimation side such as, energy consumption, precision, and speed. Furthermore, an overview of the most adequate memory architectures and interconnection networks, to aim the most suitable virtual platforms of simulation for SoC.

<p>To deploy the enormous hardware resources available in Multi Processor Systems-on-Chip (MPSoC) efficiently, rapidly and accurately, methods of Design Space Exploration (DSE) are needed to evaluate the different design alternatives. In this paper, we present a framework that makes fast simulation and performance evaluation of MPSoC possible early in the design flow, thus reducing the time-to-market. In this framework and within the Transaction Level Modeling (TLM) approach, we present a new definition of ISS level by introducing two complementary modeling sublevels ISST and ISSPT. This later, that we illustrate an arbiter modeling approach that allows a high performance MPSoC communication. A round-robin method is chosen because it is simple, minimizes the communication latency and has an accepted speed-up. Two applications are tested and used to validate our platform: Game of life and JPEG Encoder. The performance of the proposed approach has been analyzed in our platform MPSoC based on multi-MicroBlaze. Simulation results show with ISSPT sublevels gives a high simulation speedup factor of up to 32 with a negligible performance estimation error margin.</p>