Abstract. This paper addresses the formalization in higher-order logic of fixed-point arithmetic. We encoded the fixed-point number system and specified the different quantization modes in fixed-point arithmetic such as the directed and even quantization modes. We also considered the formalization of exceptions detection and their handling like overflow and invalid operation. An error analysis is then performed to check the correctness of the quantized result after carrying out basic arithmetic operations, such as addition, subtraction, multiplication and division against their mathematical counterparts. Finally, we showed by an example how this formalization can be used to enable the verification of the transition from floating-point to fixed-point algorithmic level in the signal processing design flow.

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In this paper, the authors address a delivery process with time requirements in the supply chain, stated as follows: orders launched from customers are centralized and assigned to firms' depots for the delivery process. The consideration of a depot and a set of customers belonging to different firms, is seen as a VRPTW that serves n customers using a subset of vehicles. Implemented in this article is a DSS that handles the delivering activity in the supply chain. The DSS embeds a Greedy Randomized Adaptive Search Procedure (GRASP) and Genetic components for generating promising solutions in a concurrently run time. Simulation results are conducted on Solomon's benchmarks. The DSS records very competitive results regarding state-of-the-art approaches.