This paper compares the performance of first and second order time delay tanlock loop (TDTL) based integer frequency synthesizers. Varying the order of the loop changes the locking region of the complete system and affects the locking convergence. The synthesizer divider block also affects the system stability. Depending on the division factor the system may be driven outside its locking region. This is overcome by introducing an additional block that adaptively stabilizes the loop by driving it back to within the locking region. The results achieved indicate that the adaptive integer frequency synthesizers operate satisfactorily. The second order loop has shown to give a better acquisition performance when compared with the first order loop. This is due to the zero steady state phase error exhibited by the loop.