Time-based successive approximation register (SAR) analogue-to-digital converters (ADCs) are gaining attraction in ultra-low voltage circuit design. Such ADCs typically use multi-stage voltage controlled delay lines (VCDLs) to perform voltage to time conversion in order to mitigate limited headroom of voltage signals. Although multi-stage VCDLs are used, only the outputs of the final VCDL stages are compared during bit trials. This work demonstrates that additional bit information can be extracted by scavenging timing information revealed at VCDL intermediate stages. The additional bit information can be used to accelerate the ADC conversion process or improve signal-to-noise distortion ratio (SNDR). To cope with uncertainties associated with signals from VCDL intermediate stages, an uncertainty-tolerant SAR procedure is developed. Also, this work presents techniques for adaptively selecting which intermediate stage signals to be tapped along the conversion process. The proposed techniques are applied in the design of a 0.4 V 9-bit SAR ADC in a 130 nm CMOS technology. Silicon measurement results show that with the additional information extracted from VCDL intermediate stages the conversion for the vast majority of ADC inputs can be completed in 7 or 8 clock cycles. Measurement results also demonstrate the potentials of using the intermediate stage signals to improve ADC SNDR.

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This paper presents a novel time and voltage based technique for successive approximation register (SAR) analogto-digital converter (ADC) to improve the conversion speed. By taking advantage of the fact that at low supply voltage there will be a significant difference in comparator decision time for different input voltages, the proposed technique creates multiple auxiliary voltage levels for comparison and hence eliminates the need of additional comparators for acceleration as compared with the existing methods. In addition, a digital self-learning module is also presented, which calculates the uncertainty window required for bound update in the proposed method and thus adjusts to different process corners. To validate these concepts, a 10-bit SAR ADC is designed in 130nm CMOS process with 0.5V power supply voltage. The circuit operates in both conventional and proposed modes. Simulations show that the largest number of conversion cycles is 7, hence resulting in an acceleration of 30% over the conventional scheme, while the average number of cycles is 5.58. Simulation results also demonstrate that the proposed method does not affect accuracy. Both ADC operation modes achieve SNDR (signal-tonoise distortion ratio) of 59dB, corresponding to an ENOB (effective number of bits) of 9.5-bits.

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This work presents techniques that effectively utilise comparator timing information to accelerate low-voltage successive approximation register (SAR) analogue-to-digital converter (ADC) operation. Compared to existing approaches that only exploit the prolonged comparator decision time in the events of metastability, the proposed techniques are effective in a broader voltage range and can extract more information about the voltages being compared. To cope with large variations associated with comparator delay, this work proposes robust timing measurement circuit, uncertainty-tolerant search algorithm and circuit adaptive tuning techniques. The adaptive tuning technique enables ADC to autonomously find voltage levels corresponding to the outputs of the timing measurement circuit as well as to adjust the uncertainty ranges used in the search algorithm. This eliminates the need of post-silicon calibration for the timing measurement circuits, which are typically required in existing approaches. The developed techniques are used in the design of a 9-bit 0.45 V SAR ADC circuit with a 130 nm complementary metal-oxide-semiconductor technology. Measurement results from the prototype chip indicate that for most input levels the proposed ADC completes conversion in six or seven conversion cycles. At 200 KS/s sampling rate, its power dissipation is 2.88 µW and it achieves a signal-to-noise distortion ratio of 50.66 dB with a figure of merit of 51.8 fJ/c.-s.