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Video Matting can be described as a method of extracting the foreground object from each frame of a video and composite (or transfer) it to a different background or a different video. An automatic scribbling approach based on the motion of the foreground object in a video is introduced. Probability maps (PMs) are computed by analysing the motion of object in the video. In the proposed technique the corrupted PMs are refined and reconstructed using morphological techniques. The frames are scribbled with reference to the reconstructed PMs. Closed form solution based matting technique uses the scribbled frame to yield the matte and the foreground.

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In this paper, we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP's/SoC's. With the tight schedules on all projects it is important to have a strong verification methodology which contributes to First Silicon Success. Deploy methodologies which enforce full functional coverage and verification of corner cases through pseudo random test scenarios is required. Also, standardization of verification flow is needed. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment for IP/Subsystem level verification and C/C++/Verilog based Directed Verification Environment for SoC Level Verification was used for Functional Verification. Different Verification Environments were used at IP level and SoC level. Different Verification/Validation Methodologies were used for SoC Verification across multiple sites. Verification teams were also looking for the ways how to catch bugs early in the design cycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based Reusable Verification Environment is required to avoid the problem of having so many methodologies and provides a standard unified solution which compiles on all tools. The main aim of development of this Generic and automatic verification environment is to develop an efficient and unified verification environment (at IP/Subsystem/SoC Level) which reuses the already developed Verification components and also sequences written at IP/Subsystem level can be reused at SoC Level both with Host BFM and actual Core using Incisive Software Extension (ISX) and Virtual Register Interface (VRI)/Verification Abstraction Layer (VAL) approaches. IP-XACT based tools are used for automatically configuring the environment for various imaging IPs/SoCs. Although this paper focus on Generic System Verilog Universal Verification Methodology based reusable verification environment built for imaging IPs/SoCs. Same concept can be extended for non imaging IPs/SoCs.

This paper presents a survey on various novel defect and noise detection and correction algorithms used in CMOS image sensors. This class of sensors is extremely relevant in number of applications in the areas of gaming, security, medical, automotive, high-end camera market, etc. This survey outlines the algorithms and the hardware implementation of novel defect and noise detection and correction schemes to detect and correct defective pixels, and discusses their performance and advantages in terms of their applications. Experimental results on various images illustrate the capabilities of the studied approaches.