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Profiling and parallel computing techniques in a cluster of six embedded systems with multiprocessors are introduced herein to implement a chaotic cryptosystem for digital color images. The proposed encryption method is based on stream encryption using a pseudo-random number generator with high-precision arithmetic and data processing in parallel with collective communication. The profiling and parallel computing techniques allow discovery of the optimal number of processors that are necessary to improve the efficiency of the cryptosystem. That is, the processing speed improves the time for generating chaotic sequences and execution of the encryption algorithm. In addition, the high numerical precision reduces the digital degradation in a chaotic system and increases the security levels of the cryptosystem. The security analysis confirms that the proposed cryptosystem is secure and robust against different attacks that have been widely reported in the literature. Accordingly, we highlight that the proposed encryption method is potentially feasible to be implemented in practical applications, such as modern telecommunication devices employing multiprocessors, e.g., smart phones, tablets, and in any embedded system with multi-core hardware.

A new embedded chaotic cryptosystem is introduced herein with the aim to encrypt digital images and performing speech recognition as an external access key. The proposed cryptosystem consists of three technologies: (i) a Spartan 3E-1600 FPGA from Xilinx; (ii) a 64-bit Raspberry Pi 3 single board computer; and (iii) a voice recognition chip manufactured by Sunplus. The cryptosystem operates with four embedded algorithms: (1) a graphical user interface developed in Python language for the Raspberry Pi platform, which allows friendly management of the system; (2) an internal control entity that entails the start-up of the embedded system based on the identification of the key access, the pixels-entry of the image to the FPGA to be encrypted or unraveled from the Raspberry Pi, and the self-execution of the encryption/decryption of the information; (3) a chaotic pseudo-random binary generator whose decimal numerical values are converted to an 8-bit binary scale under the VHDL description of m o d ( 255 ) ; and (4) two UART communication algorithms by using the RS-232 protocol, all of them described in VHDL for the FPGA implementation. We provide a security analysis to demonstrate that the proposed cryptosystem is highly secure and robust against known attacks.