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This paper presents a complete method for automatically translating VHDL-AMS behavioral-specifications of analog systems into op amp level net-lists of library components. We discuss the three fundamental aspects, that pertain to any behavioral synthesis environment: the specification language, the rules for compiling language constructs into a technology-independent, intermediate representation, and the synthesis (mapping) of representations to net-lists (topologies) of library components, so that performance constraints are satisfied. We motivate the effectiveness of the method by presenting our synthesis results for 5 examples.

Table of Figures viii Nomenclature xiv vi 4.2 Iterative Improvements to the Procedure 4.3 Procedure for the Improved Bayesian Algorithm 4.4 Model with Two or More Dominant Frequencies 4.5 Smart Algorithm 4.6 Comparison to Spline Fit Estimate: 5. The Pulse Algorithm (nPA) 41 5.1 Need for a Better Instantaneous Speed Estimation Process 5.2 Analysis of the Cause for Fluctuations in the Instantaneous Speed Curve