A technique for fabricating Au-rich nanoparticles via phase separation and subsequent oxidation of amorphous Au25Si75 sputtered thin films is presented. Nanoparticles formed in this manner are surrounded by SiO2 and have an average diameter of 2.88nm with an aerial density of 1.9×1012cm−2. Au-rich nanoparticles are incorporated into capacitor structures and the capacitance-voltage behavior is characterized. Significant hysteresis is observed and the flat-band voltage shift is attributed to charge storage due to the presence of the metal nanoparticles.

Articles you may be interested inPhotoluminescence properties and crystallization of silicon quantum dots in hydrogenated amorphous Si-rich silicon carbide films This paper discusses the self-assembled formation of monodisperse gold-rich nanoparticles and associated crystalline silicon nanostructures. Multilayer films comprising of amorphous Au 25 Si 75 and amorphous silicon were grown via dc magnetron sputtering and subsequently annealed under varying thermal conditions. The films were characterized by electron microscopy before and after the thermal anneal. Thermal decomposition of the multilayer films results in the metal induced crystallization of amorphous silicon, as well as the formation of uniform Au-rich nanoparticles. Further annealing did not alter the size or position of the nanoparticles, indicating that the particles are too small to induce further silicon crystallization. Through thermodynamic modeling, two mechanisms are shown to be viable means for nanoscaled size selection. The first mechanism entails crystallization of Au 25 Si 75 followed by metal induced crystallization of amorphous silicon, while the second utilizes spinodal decomposition of Au 25 Si 75 to select a single nanoparticle radius.

This article describes the electrical and physical properties of polysilicon doped with novel N+ and P+ screen printed inks using a thermally activated process. Unique ink formulations for N and P type doping of silicon are evaluated in volume production in order to enable a low cost, high throughput process. Inks can be used with multiple substrate types and form factors. The concentrated doping source combined with thermal drive in and activation results in degenerately doped layers of polysilicon. Inks are semiconductor grade which is demonstrated by their use in fabricating high mobility, low leakage Thin Film Transistor (TFT) devices on 300 mm stainless steel substrates. Reproducible sheet resistance values (700 A polysilicon) can be engineered from levels typically ranging from 200 - 2000 ohm/sq. The additive approach substitutes the use of high capital cost ion implantation and lithography processes. The ink formulation results in screen printed widths capable of ranging from 100-300 um. As both N and P type layers can be printed adjacent to each other, it is critical to prevent cross doping using surface preparation techniques. Post doping cleaning of surfaces can be achieved in-situ or by plasma removal depending on process integration and product considerations. Reproducibility and uniformity data to demonstrate manufacturability in a production environment is shown. In summary, a simple, low cost, high throughput additive process based on proprietary inks that can be used in multiple product flows (CMOS TFT, Solar etc.) is demonstrated.

Stainless steel substrates enable a combination of low cost, flexibility, durability, high processing temperatures, and sub-100 um thickness making it well suited for sheet based and roll-to-roll processing. NFC (13.56 MHz) based circuits using high performance polysilicon TFTs on steel sheets have been manufactured using a hybrid printed process in a production environment. The process scheme utilizes a hybrid, additive materials approach encompassing low cost manufacturing steps such as slot die coating and screen printing of silicon and dopant inks to enable a high throughput, low cost, manufacturing flow. This paper describes the approach for migrating from a sheet-based hybrid process flow to a R2R-based process. A comparison of substrate choices and considerations for R2R process integration is presented. A sensitive electrical method for evaluating the feasibility of R2R-based process integration schemes and materials selection is presented. MIM capacitor leakage, TFT device characteristics, NFC circuit performance, and defect density considerations are shown as a function of steel substrate bending, down to a diameter of 0.75 inches. Electrical characteristics and optical inspections show no measurable change to insulator characteristics, demonstrating a high degree of flexibility and overall device and process capability for R2R processing.

Laser crystallized CMOS TFTs were fabricated on thin 300 mm stainless steel substrates using novel coated silicon in a Printed Dopant PolySilicon (PDPS) process-flow [1]. Silicon ink will be a key building block for low-cost, continuous large-area coating or printing in very highvolume roll-to-roll manufacturing.RF devices with PECVD-equivalent TFT characteristics using semiconductor-grade inks are routinely fabricated using this process. This technology is foundational to RF (13.56MHz), display and integrated sensor system circuits on thin, large-area flexible and durable substrates.