We introduce in this paper a new FPGA-based Maximum Power Tracker for photovoltaic systems. The developed approach targets to modify the perturb and observe in view of reaching rapid tracking and achieving excellent accuracy, while keeping the stability performance and the reduced complexity. To perform this improvement, an automatic and smart two steps switcher is integrated, in addition inputs FIR filters are incorporated. Therefore, a high sampling frequency is attained, and consequently the tracking speed is improved. MATLAB simulations and the Xilinx FPGA implementation results show that the improved approach reaches a performance very close to the recently published MPPT methods, with lesser complexity. Keyword:FPGA implementation Maximum power point tracking Perturb and observe Photovoltaic systems

This paper presents an efficient architecture for different mathematical models for optimal design of a photovoltaic system using Xilinx System Generator (XSG). This architecture offers an alternative through a graphical user interface that combines MATLAB/Simulink and XSG and explores important aspects of the experimental implementation. The use of the Xilinx generator for calculating the power output of a photovoltaic system reduces the complexity and structural design and also provides an additional feature for materializing the system.

This paper proposes an efficient high-order finite impulse response (FIR) filter structure for field programmable gate array (FPGA)-based applications with simultaneous digital signal processing (DSP) and look-up-table (LUT) reduced utilization. The real-time updating of the filter coefficients is also put into perspective. In order to perform these objectives, both the speed and the structure of FPGA are efficiently exploited. The gap between the required input sampling frequency and the FPGA allowed maximum frequency is managed to achieve additional computing sequences. Furthermore, the special structures of the FPGA Look-up-table Shift-Register (LUT-SR) and their internal connections are fully employed for pipelining and selecting the input samples. The FPGA Block RAMs (BRAMs) are employed for handling the reconfigurable filter coefficients, and the FPGA DSP slices are associated for computing the output data of the BRAMs and the multiplexers. To synchronize the BRAM unit addressing with the LUT multiplexer selection, a single unit is used for simultaneous control. The obtained results show that the proposed reconfigurable 16tap FIR filter offers reductions of 79.3% and 74.4% of slice utilization over the hybrid variable size partitioning (VP-Hybrid) based structure and the Radix-2 r based structure, respectively when implemented on a Xilinx Spartan-6 XC6SLX45 FPGA. Moreover, an improvement of efficiency is achieved compared to all reputed FPGA-based architectures.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.