In this paper, we propose the implementation of multiple defect-tolerant techniques on an SRAM-based FPGA. These techniques include redundancy at both the logic block and intra-cluster interconnect. In the logic block, redundancy is implemented at the multiplexer level. Its efficiency is analyzed by injecting a single defect at the output of a multiplexer, considering all possible locations and input combinations. While at the interconnect level, fine grain redundancy is introduced which not only bypasses defects but also increases routability. Taking advantage of the sparse intra-cluster interconnect structures, routability is further improved by efficient distribution of feedback paths allowing more flexibility in the connections among logic blocks. Emulation results show a significant improvement of about 15% and 34% in the robustness of logic block and intracluster interconnect respectively. Furthermore, the impact of these hardening schemes on the testability of the FPGA cluster for manufacturing defects is also investigated in terms of maximum achievable fault coverage and the respective cost.

This paper presents an improved cluster-based Mesh architecture. This architecture has a depopulated intracluster interconnect, and presents a new hierarchical topology for the switch box which unifies a downward and an upward unidirectional networks. Experimental results of 20 MCNC benchmarks show that density is improved and interconnect area requirement is reduced by 42% compared to the cluster-based VPR architecture.

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International audienceNowadays, modern FPGA architectures are mainlyorganized in clusters of configurable logic resources connected togetherby depopulated interconnect. However, cluster architectureorganization and size versus inter and intra-cluster interconnectarchitectures is an ongoing optimization process, as it severelyimpacts the routability, area saving, testability and the overallrobustness of a given FPGA. This paper addresses a thoroughanalysis of the cluster size impact on area and routability ofthe cluster as well as on its testability and inherent robustness. Benchmark circuits are synthesized in a range of cluster sizes(number of logic blocks per cluster) 4, 6, 8, 10 and 12 to identifythe optimum one in terms of area and routability. Then, theoverall cluster testability and its respective cost is examinedusing BIST algorithm developed for this purpose. To completethe analysis, cluster size impact on the robustness of the clusterlogic and the intra-cluster interconnect is assessed by logicalmasking ability. Results show that the cluster of size 12 offers abetter routability at relatively less test cost along with a better robustness