In this paper, a high speed residue to binary converter for three moduli set {2n - 1, 2n + 1, 2n} is presented in this paper, which uses two-part RNS and is based on mixed radix conversion (MRC). By using two-part RNS, the number of modulus in each part decreases; therefore the complexity of reverse converter is reduced. Also, the architecture of the proposed converter is based on subtractors and Multiplexers which are suitable for VLSI implementation. Reducing the number of modulus and simplifying the structure of the proposed converter lead to improvement of the latest presented converter in terms of area and delay. In order to obtain an accurate comparison, the proposed converter and the fastest designs were implemented on Xilinx 12.1 FPGA simulator, area and delay of each converter was measured for various word widths up to 64-bit. As the results indicated the novel proposed method has better Area and conversion time comparing to the previous designs.