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True-time delay (TTD) cells are used in timed array receivers for wideband multi-antenna topologies. TTD cells are divided into two major categories: silicon-based and non-silicon-based structures. Non-silicon-based structures have very good bandwidth but are bulky in the below 10 GHz frequency band. Silicon-based TTD cells are much more compact and better candidates for integrated circuit (IC) design. Passive and active approaches are the two ways to have a silicon-based TTD cell. Passive TTD cells are built by transmission lines (TL), artificial transmission lines (ATL), and LC ladder networks. Their power consumption is very low, and the delay bandwidth is good, but they are still bulky at low frequencies like below 5 GHz applications. Active all-pass filters as TTD cells are presented for these issues. In this chapter, we will discuss the challenges of inductor-based TTD cells. Then, inductor-less TTD cells are presented to address some of the previous structure’s issues. Finally, we will talk about these structures’ challenges as well. Then, the nonidealities effects on the TTD cell’s performance are investigated, and the body bias technique is presented to address these issues.

A true-time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1-5 GHz applications is presented. Process variations, ageing effects, field variations, and other non-idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor-less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non-idealities, while delay variation improves more than 3� times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S 11 and S 22 parameters are lower than −10 dB in the 1-5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW. K E Y W O R D Sall-pass filter, active filters, analogue integrated circuits, CMOS analogue integrated circuits, continuous time systems, integrated circuit design, low-power electronics, radio frequency filters, Timed array system, True-Time-Delay cellThis is an open access article under the terms of the Creative Commons Attribution-NonCommercial-NoDerivs License, which permits use and distribution in any medium, provided the original work is properly cited, the use is non-commercial and no modifications or adaptations are made.