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Integration of RF transceiver blocks along with the digital signal processing part in CMOS is becoming the trend in the semiconductor industry for lower cost and smaller form factor. Nowadays, the interest is even growing towards implementing the RF PA in CMOS technology. Cost reduction, diversifying means of fabrication and the addition of performance enhancement circuitry are the main reasons behind this growing interest. However, implementing RF PAs for 3G/4G standards in CMOS is quite challenging: The low breakdown voltage of nanoscale CMOS causes a ruggedness problem at typical average output power (P avg ) levels of 26dBm or more. In [1,2], power-combining techniques were used to reach PA output power (P out ) of 33dBm. However, amplification of signals with high peak-to-average-power-ratio (PAPR) requires also a high degree of linearity. Significant AM-PM distortions caused by the voltagedependent parasitics are a fundamental problem in CMOS PAs. Thus far, predistortion is used to meet EVM requirements [2]. To overcome these challenges, this work presents a new class of operation, termed as Class-O, demonstrated by the design and the measurement of a single-stage PA implemented in 0.13μm CMOS and operating from a 3.3V supply.

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