Semiconductor Companies and Industries soar high as the trend for electronic gadgets and devices increases. Transition from “manual” to “fully automatic” application is one of the advantages why consumer adapt to changes and prefer electronic devices as one of daily answers. Individuals who admire these electronic devices often ask how they are made. As we look inside each device, we can notice interconnected microchips commonly called IC (Integrated Circuit). These are specially prepared silicon wafers where integrated circuit are developed. Commonly, each device is composed of numerous microchips depending on the design and functionality IC production is processed from “front-end” to “back-end” assembly. Front-end assembly includes wafer fabrication where electrical circuitry is prepared and integrated to every single silicon wafers. Back-end assembly covers processing the wafer by cutting into smaller individual and independent components called “dice”. Each dice will be placed into Leadframe, bonded with wires prior encapsulating with mold compounds. After molding, each IC will be cut through a process called singulation. Afterwards, all molded units are subjected for functional testing. Dice is central to each IC; it is where miniature transistor, resistor and capacitor are integrated to form complex small circuitry in microchips. Pre-assembly (Pre-assy) stations have the first hand prior to all succeeding stations. Live wafers are primary direct materials processed in these stations. Robust work instruction and parameter must be practiced during handling and processing to avoid gross rejection and possible work-related defects. The paper is all about the challenges to resolve and improved the backside chippings in 280um wafer thickness in mechanical dicing saw. The conventional Mechanical dicing process induce a lot of mechanical stress and vibration during the cutting process which oftentimes lead to backside chipping and die crack issues. However, backside chippings can mitigate with proper selection of parameter settings and understand the silicon wafer properties.
Nowadays, semiconductors and electronics are becoming part of our everyday activities. As the Integrated circuits become more useful to people, it also requires more function, which contain more complex and compact components. Aligned to this package requirement, the more challenging it become to package development as Silicon technology becomes more critical and complex from bare silicon to conventional MOS technology to Ultra Low-K, which requires a different strategy. The new process development in the Semiconductor industry is a necessity to cope up with these new technologies. Low-k devices always pose a big challenge in achieving good dicing quality. This is because of the weak mechanical properties of the low-k dielectric material used. Mechanical Sawing is the most popular cutting method for silicon, but with Ultra low-K technology, using mechanical sawing will lead to various sawing defects such as chippings and delamination [1,2]. These leads to the introduction of Laser Grooving to get rid of these dilemmas. Laser grooving uses heat to eradicate metals on this very thin metal wafer dicing saw streets in preparation for wafer saw process to prevent topside chippings and delamination/metal peel off [3]. These defects are not acceptable especially since the product application is a chip card. Since chip cards must be flexible and durable, they require higher die and package strength to serve its purpose. To achieve such package requirement, different method was evaluated such as standard mechanical dicing, standard Laser Grooving and the PI laser groove. The paper will discuss how we were able to achieve the quality requirement for Ultra Low-K and at the same time eliminating top reject contributor during startup of this device.
Today, semiconductor world is becoming more inclined to thinner Integrated Circuit (IC) packages. IC packages will require thinning of the internal configuration of the package, which involves the die or the wafer and the adhesive material, which is the Die Attach Film (DAF). Aligned to this, as wafers goes thinner it becomes more of a challenge in process development especially during its preparatory stages, such as wafer back grinding and sawing processes. As the die becomes smaller and thinner wafer sawing process should have minimum effect on the mechanical integrity of the silicon so as not to alter its quality. New technologies were introduced so as to adopt to this development trend, one of this is the Dicing Before Grinding (DBG). Compared to the normal wafer preparation process that is wafer back grinding before wafer sawing, DBG flow is wafer sawing first prior wafer back grinding processes. The application of DBG technology eliminates the mechanical draw backs of the conventional wafer sawing process. In addition, with the use of DAF for thinner packages, DBG was developed together with the Die Attach Film (DAF) cutting solution, which is Laser DAF Cutting. DAF are separated using Laser as a cutting medium to address potential processability problems that may occur on the conventional mechanical blade saw. The paper discuss the Laser DAF cut development that covers the Design of Experiments (DoE) to understand the different characteristics of Laser DAF solution and be validated through actual simulation and wafer processing. The paper will also cover the interaction of different DAF thicknesses and Laser DAF parameters in order to define the critical characteristics so as to understand the behavior of different laser DAF parameters in achieving optimal DAF cutting process responses.
Glass material used on a semiconductor device for isolating currents are one of the new breakthroughs of the modern world. Challenges are inevitable due to its complex characteristics and unique appearance. The study focuses on the phenomenon of reject glass die unrecognized, picked and bonded by die attach machine on good units of the semiconductor quad-flat no-leads (QFN) device in focus. This QFN device utilizes glass die as interposer on two active dice that separates the dielectric current of each die. During die attach process, machine photo recognition system failed to recognize and detect the glass die reject marking due to its unique transparent design and will be attached on good units. Thus, resulting to gross rejection and low process yield. Practical solutions to prevent the said phenomenon are simulated and determined by performing selection of variables like the contrast of the reject mark related to the product structure and compatibility through statistical analysis. The improvement drives to promote process robustness and scrap reduction that will help the manufacturing to be competitive through innovative resolutions on problems.
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