Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all arithmetic components are reused. By introducing a new composite field, the S-Box structure is also optimized. An extremely small size of 5.4 Kgates is obtained for a 128-bit key Rijndael circuit using a 0.11-µm CMOS standard cell library. It requires only 0.052 mm 2 of area to support both encryption and decryption with 311 Mbps throughput. By making effective use of the SPN parallel feature, the throughput can be boosted up to 2.6 Gbps for a high-speed implementation whose size is 21.3 Kgates.

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The quantitative performance indicators of Physical Unclonable Functions (PUFs)-Randomness, Steadiness, Correctness, Diffuseness and Uniqueness-are strictly defined and applied to the evaluation of 45 arbiter PUFs on Virtex-5 FPGAs. The indicators effectively reflect the characteristics of PUFs ranging from 0 to 1 with 1 being the highest performance. The indicators enable the easy measurement and intuitive understanding of PUF performances. The experimental results shows that the arbiter PUFs have excellent overall intradevice performances though a slight bit bias is indicated. The inter-device performance is moderate and will suffice for the practical use of PUFs for device authentication and so on. Additionally, the reliability of the obtained PUF performances is statistically discussed in terms of the Confidence Interval and the number of devices. This paper presents in detail the definitions of the performance indicators and the quantitative and statistical evaluation results of the arbiter PUFs.

Abstract. Reducing the power consumption of AES circuits is a critical problem when the circuits are used in low power embedded systems. We found the S-Boxes consume much of the total AES circuit power and the power for an S-Box is mostly determined by the number of dynamic hazards. In this paper, we propose a low-power S-Box circuit architecture: a multi-stage PPRM architecture over composite fields. In this S-Box, (i) the signal arrival times of gates are as close as possible if the depths of the gates from the primary inputs are the same, and (ii) the hazard-transparent XOR gates are located after the other gates that may block the hazards. A low power consumption of 29 mW at 10 MHz using 0.13 mm 1.5V CMOS technology was achieved, while the consumptions of the BDD, SOP, and composite field S-Boxes are 275, 95, and 136 mW, respectively.

Abstract. This paper describes high-resolution waveform matching based on a Phase-Only Correlation (POC) technique and its application for a side-channel attack. Such attacks, such as Simple Power Analysis (SPA) and Differential Power Analysis (DPA), use a statistical analysis of signal waveforms (e.g., power traces) to reduce noise and to retrieve secret information. However, the waveform data often includes displacement errors in the measurements. The use of phase components in the discrete Fourier transforms of the waveforms makes it possible to estimate the displacements between the signal waveforms with higher resolution than the sampling resolution. The accuracy of a side-channel attack can be enhanced using this high-resolution matching method. In this paper, we demonstrate the advantages of the POC-based method in comparison with conventional approaches through experimental DPA and Differential ElectroMagnetic Analysis (DEMA) against a DES software implementation on a Z80 processor.