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Currently, fabrication processes for superconductive integrated circuits are moving to multiple wiring and shielding layers, some of which are placed below the main ground plane (GP) and device layers. The Advanced Industrial Science and Technology advanced process (ADP2) was the first such multi-layer Nb process with planarized passive transmission line and GP layers below the junction layer, and is at the time of writing still the most developed. This process allows complex circuit designs, and accurate inductance extraction helps to push the boundaries of the layouts possible. We show that the position of ground connections between ground layers influences the inductance of structures for which these GPs act as return path, and that this needs to be accounted for in modelling. However, due to the number of wiring layers and GPs, full layout modelling of large cells causes long calculation times. In this paper we discuss methods with which to reduce model size, and calibrate InductEx calculations using these methods against measured results. We show that model reduction followed by calibration results in fast calculation times while good accuracy is maintained. We also show that InductEx correctly handles coupling between conductors in a multi-layer layout, and how to model layouts to gauge unwanted coupling between power lines and single flux quantum electronics.

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