Semiconductor nanowire lasers are considered promising ultracompact and energy-efficient light sources in the field of nanophotonics. Although the integration of nanowire lasers onto silicon photonic platforms is an innovative path toward chip-scale optical communications and photonic integrated circuits, operating nanowire lasers at telecom-wavelengths remains challenging. Here, we report on InGaAs nanowire array lasers on a silicon-on-insulator platform operating up to 1440 nm at room temperature. Bottom-up photonic crystal nanobeam cavities are formed by growing nanowires as ordered arrays using selective-area epitaxy, and single-mode lasing by optical pumping is demonstrated. We also show that arrays of nanobeam lasers with individually tunable wavelengths can be integrated on a single chip by the simple adjustment of the lithographically defined growth pattern. These results exemplify a practical approach toward nanowire lasers for silicon photonics.

Selective area epitaxy (SAE) provides the path for scalable fabrication of semiconductor nanostructures in a device-compatible configuration. In the current paradigm, SAE is understood as localized epitaxy and is modelled by combining planar and self-assembled nanowire growth mechanisms. Here we use GaAs SAE as a model system to provide a different perspective. First, we provide evidence of the significant impact of the annealing stage in the calculation of the growth rates. Then, by elucidating the effect of geometrical constraints on the growth of the semiconductor crystal, we demonstrate the role of adatom desorption and resorption beyond the direct-impingement and diffusion-limited regime. Our theoretical model explains the effect of these constraints on the growth, and in particular why the SAE growth rate is highly sensitive to the pattern geometry. Finally, the disagreement of the model at the largest pitch points to non-negligible multiple adatom recycling between patterned features. Overall, our findings point out the importance of considering adatom diffusion, adsorption and desorption dynamics in designing the SAE pattern to create predetermined nanoscale structures across a wafer. These results are fundamental for the SAE process to become viable in the semiconductor industry.

III–V integration on Si(100) is a challenge: controlled vertical vapor liquid solid nanowire growth on this platform has not been reported so far. Here we demonstrate an atypical GaAs vertical nanostructure on Si(100), coined nanospade, obtained by a nonconventional droplet catalyst pinning. The Ga droplet is positioned at the tip of an ultrathin Si pillar with a radial oxide envelope. The pinning at the Si/oxide interface allows the engineering of the contact angle beyond the Young–Dupré equation and the growth of vertical nanospades. Nanospades exhibit a virtually defect-free bicrystalline nature. Our growth model explains how a pentagonal twinning event at the initial stages of growth provokes the formation of the nanospade. The optical properties of the nanospades are consistent with the high crystal purity, making these structures viable for use in integration of optoelectronics on the Si(100) platform.