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In this paper a two-stage 2-GHz GaN HEMT amplifier with 15-W output power, 28-dB power gain, and 70% poweradded efficiency (PAE) is presented.The power stage is designed to operate under class F conditions. The driver stage operates under class F 1 conditions and feeds the power stage with both fundamental and second harmonic components. The inter stage matching is designed to target a quasi-half sine voltage shape at the intrinsic gate port of the power stage. The goal is to reduce aperture angle of the power stage and get PAE improvements over a wide frequency bandwidth.In addition to the amplifier design description, this paper reports original time-domain waveform measurements at internal nodes of the designed two-stage power amplifier using calibrated high-impedance probes and large signal network analyzer. Furthermore, waveform measurements recorded at different frequencies show that aperture angle remains reduced over large frequency bandwidth. In this study, a PAE greater than 60% is reached over 20% frequency bandwidth. Index Terms-Aperture angle, classes F and F 1 , GaN power amplifier (PA), power-added efficiency (PAE), waveform measurements.

This paper presents a technique to improve the power added efficiency (PAE) of GaN power amplifiers by an appropriate shaping of the gate source voltage waveform. The proposed technique is based on second harmonic injection at the transistor input. It is applied here to a 15W GaN HEMT die from Cree that has been characterized using an harmonic load pull test bench at L-band. The work reported here focuses on experimental gate-source voltage waveform shaping and its impact on PAE performances. An original aspect concerns calibrated time domain waveform measurements and shaping that are performed and investigated simultaneously at both input and output ports of the transistor under test close to intrinsic accesses. Measurement results performed at 2GHz validate optimized operating conditions derived from theoretical analysis and circuit simulations. For a fixed input bias voltage (close to pinch off voltage in our case), significant efficiency improvements are obtained when the positive half wave of the gate-source voltage is sharpened. Best and worst cases are examined respectively and show 25 point PAE difference at saturated power.

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