There are many unique challenges associated with providing remote access to space experimental payloads. The limited bandwidth to the space craft, the inability to physically monitor and probe the payload, and the management of access time for various researchers working on the project all compound to create a challenging work environment. The Configurable Fault Tolerant Processor (CFTP) project aims to alleviate many of the difficulties associated with remote payload operation. We have made use of modular FPGA design, which allows us to transfer only small application modules rather than full configuration files. This dramatically reduces the bandwidth required to upload new applications as we discover new experiments for the CFTP after launch. Another unique aspect of the CFTP project is the collaborative effort in its development. We must manage access time for universities and research institutions across the country for running experiments on the CFTP, downloading CFTP documents, and analyzing telemetry after launch.
Abstract-A methodology to quantify the impact of SEEs on complex digital devices has been developed. This methodology is based on the SEE State-Transition Model and was validated by radiation testing of a complex digital device.
This research explores the employment of Reduced Precision Redundancy (RPR) as a powersaving alternative to traditional Triple Modular Redundancy (TMR). This paper focuses on the details of RPR implementation and the effect of RPR fault tolerance on the performance of spacecraft systems. RPR-protected system performance is evaluated using a signal-to-noise ratio analogy developed with MATLAB and Simulink computational tools. This research demonstrates that RPR is an effective fault tolerance approach for arithmetic operations Experimental results show that the benefit of RPR increases with the complexity of the operation to which it is applied.System performance simulations demonstrate that RPR provides very good recovery from errors caused by SEE in spacecraft systems.
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