Newest technologies of integrated circuits fabrication allow billions of transistors arranged in a single chip enabling to implement a complex parallel system, which requires a high scalable and parallel communication architecture, such as a Network-on-Chip (NoC). These technologies are very close to physical limitations increasing faults in manufacture and at runtime. Thus, it is essential to provide a fault recovery mechanism for NoC operation in the presence of faults. The preprocessing of the most probable fault scenarios and flits retransmission capability enable to anticipate the calculation of deadlock-free routings, reducing the time necessary to interrupt the system in a fault occurrence and maintaining links operating with retransmission capability. This work proposes a smart decisions mechanism for errors on NoC links, which is composed of a hardware part implemented into the links and routers, and a software part implemented inside an operating system kernel of each processor. The mechanism defines thresholds where is better to reconfigure the NoC or to retransmit flits with errors. Experimental results, with several NoC sizes and some error models, suggest when is better to reconfigure the NoC and when is better to maintain some links operating with eventual faults.

Network-on-Chip (NoC) is a power architecture that emerged to solve communication issues present in modern Systems-on-Chip (SoCs). NoC based architectures are very scalable and offer high levels of communication parallelism, among other features. Every efficient NoC implementation requires several design steps to accomplish indices of performance. Although there are many system level models, high-level models for NoC are representative in the context of design since they provide fast and accurate analysis, with low modeling effort, for further VHDL implementations. This work proposes a NoC model based on a Timed Colored Petri Net (TCPN) that computes performance indices seamlessly. Network latency and buffer occupation are of special interest in our approach as they represent the key indices when assessing NoC performance. As results, we have validated and refined the model of a 5×5 mesh NoC comparing its indices with equivalent VHDL RTL description under synthetic and real traffic situations. The proposed model is capable of analyzing the influence of the router service time on the average latency time, enabling internal NoC evaluation to optimize buffer length. Simulation results demonstrate the model suitability for latency evaluation with time estimation errors often below 1%. Furthermore, this paper discusses the effort required to extend the model with other NoC architectural features. We conclude that the use of a TCPN model of NoC generates accurate results providing as much detailed information as their equivalent experiments using VHDL description.