Abstract-For portable applications, long battery lifetime is the ultimate design goal. Therefore, the availability of battery and voltage converter models providing accurate estimates of battery lifetime is key for system-level low-power design frameworks. In this paper, we introduce a discrete-time model for the complete power supply subsystem that closely approximates the behavior of its circuit-level continuous-time counterpart. The model is abstract and efficient enough to enable event-driven simulation of digital systems described at a very high level of abstraction and that includes, among their components, also the power supply. The model gives the designer the possibility of estimating battery lifetime during system-level design exploration, as shown by the results we have collected on meaningful case studies. In addition, it is flexible and it can thus be employed for different battery chemistries.

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In this paper, we suggest hardware-assisted data compression a s a t o ol for reducing energy consumption of core-based e m b edded systems. We propose a novel and e cient architecture f o r on-the-y data compression and decompression whose eld of operation is the cache-to-memory path. Uncompressed c ache lines are c ompressed b efore they are written back to main memory, and decompressed w h e n c ache re lls take place. We explore two classes of compression methods, pro le-driven and di erential, since they are c h a r acterized b y c ompact HW implementations, and we compare their performance to those provided by some state-of-the-art compression methods (e.g., we have considered a few variants of the Lempel-Ziv encoder). We present experimental results about memory tra c and energy consumption in the cache-to-memory path of a core-based system running standard b enchmark programs. The achieved average energy savings range from 4.2% to 35.2%, depending on the selected c ompression algorithm.