A digital PWM voltage mode controller integrated circuit (IC) for high-frequency dc-dc switching converters achieving virtually minimum possible, i.e. optimum, output voltage deviation to load transients is introduced. The IC is implemented with simple hardware, requiring small silicon area, and can operate as a single-phase or a two-phase controller. To minimize the area and eliminate known mode transition problems of the optimal response controllers, two novel blocks are combined. Namely, an asynchronous track-and-hold analogto-digital converter (ADC) and a "large-small" signal compensator are implemented. The ADC utilizes a pre-amplifier and only four comparators having approximately eight times smaller silicon area and power consumption than an equivalent windowed flash architecture. The "large-small" signal compensator consists of two parts, a digital PID minimizing small variations and a zero-current detection-based compensator suppressing large load transients. The large-signal compensator requires no extra calculations and has a low sensitivity to parameter variations. It utilizes a synchronization algorithm and the PID calculation results to obtain a bumpless mode transition and stable response to successive load transients. The IC occupying only 0.26 mm 2 silicon area is implemented in a CMOS 0.18µm process and its minimum deviation response is verified with a single and dual-phase 12 V-to-1.8 V, 500 kHz 60/120 W buck converter.I.

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+ vout(t) Load L clk _ Vin Digital Compensator e[n] vref (t) + ∆ic[n] R S Q clk Programmable Dead-time Pgate Ngate Pen[1] Ts Charge Pump DAC Windowed ADC cmp Gate-Swing Scaling Circuit Pgate PFM Controller ton [5:0] c(t) ic[n] gssc_sl<2:0> seg_sl<2:0> ON CHIP _ Sense FET c1(t) c2(t) Scan Chain PC Interface _ + vc(t) Blanking Time Efficiency Optimization PFM_en vsense(t) Ngate c1(t) c2(t) gssc_en Fig.1:Integrated mixed-signal CPM IC.Abstract-This paper introduces a mixed-signal peak currentprogrammed mode controlled 10 MHz dc-dc converter integrated circuit (IC) for low-power applications. The IC combines segmented power transistors, gate drivers and the main functional blocks of a multi-mode controller. Based on the information about the peak transistor current, obtained from the voltage loop, the controller instantaneously changes the number of segments, gate drive voltage, or switches to pulse-frequency modulation, such that for each operating point efficiency is optimized. To obtain reliable operation at such a high switching frequency and achieve efficiency optimization novel architecture of gate swing circuit is combined with modifications of known designs of other functional blocks. Experimental verification of a 0.6 W buck converter IC, fabricated in a 0.13 m process, demonstrate the peak efficiency of an 83%, near time-optimal dynamic response, and up to a 20% efficiency improvement due to the action of the efficiency optimization controller.

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