A fault coverage analysis has become an important tool to evaluate the testability of developing circuits and to come up with an effective test plan. However, the fault coverage analysis of analog circuits has not gained much attention due to the long fault simulation time and the absence of widely accepted fault models. This paper presents an efficient framework for the analog fault coverage analysis to provide repeatable and predictable analog test metrics. The presented method uses a defectbased analysis method in which faults are modeled at a transistor-level to examine faulty behavior in a structural way. In order to conduct the defect-based fault simulation in a manageable time, we develop a mixed-mode fault simulation flow which uses both behavioral-level HDL (Hardware Description Language) model and transistorlevel SPICE model simultaneously. Also, the information of transistor geometry is used in the analysis to reflect the different defect probabilities of transistors of various sizes. Our method was applied to a full-chip level fault analysis of a commercial mixed-signal IP, and the analysis result shows a good correlation with an actual post-silicon test data.