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In-line DICD control is universally used in wafer fabs to ensure on-target FICD and to monitor process fluctuation. However, how to set up an optimal DICD target sometimes becomes ambiguous as the device dimension shrinks and various photo-and etch-bias begin to emerge. In this paper, we have investigated the root cause of photo-bias and found that for i-line resist with pattern dimension smaller than O.45im, the so-called photo bias is largely caused by resist profile change. From resist cross section pictures we verify that the in-line DICD measurement usually deviates from the resist bottom CD and the deviation is resist profile dependent. Based on this understanding, we present an in-line DICD control strategy that is more efficient in terms of resist process characterization and requires no CD-SEM measurement algorithm change.

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