Summary The fault current level in distribution systems has increased in the last years mainly due to the energy consumption is in the limit of the production capacity and also the insertion of distributed generation, since the short circuits happen very closer to the generators now. In addition to this, most of the power substations were designed decades ago, so their equipment is overcome, and they may be damaged in a fault occurrence. To effectively protect the settled equipment or to avoid high investment costs in replacing them, one possible solution is to install a solid‐state fault current limiter (SSFCL), which may reduce the fault current to a value under the supported level. In this context, this work proposes the development of two kinds of SSFCLs: series‐switched reactor and resonant circuit. These devices were designed and compared experimentally in bench prototypes. The measurements showed that both topologies could reduce the fault current from 600 APEAK to 75 APEAK. Both SSFCL‐tested configurations were implemented using silicon controlled rectifier or insulated gate bipolar transistor. The results present the comparison between them, showing the impact in the first semi‐cycle current profile, depending on the type of semiconductor switch adopted. This article also proposes a fault detection algorithm evaluated through digital implementation in a microcontroller. The algorithm detects the fault by the instantaneous current value and its derivative, using a control strategy that avoids false detection due to measurement noises. The theoretical analysis and results are useful contributions to support the SSFCL topology choice regarding its application.

Power systems are becoming more interconnected and complex. The distributed generation expands and spreads across the grids, reducing the distance between the load and the generation. In addition, several substations are aging after decades of operation and their equipment struggle to sustain the ever increasing fault levels. In this context, the fault current limiter (FCL) arrived as a solution to mitigate this problem. Considering the FCL devices, the resistive superconducting FCL (R-SFCL) is the most mature technology with potential to be produced in mass scale, due to its ability to quickly change its impedance during a fault current and its high current density capacity. In this paper, a novel R-SFCL topology is presented, which has an unique design that allows a compact size and the possibility of modulated assembly. These characteristics enable setups for various voltage and current levels. One advantage of this topology is the compromise between volume and high heat exchange that can reduce the recovery time under load. One bench prototype was modeled using the thermal–electrical analogy implemented in ATPDraw, tested in two different labs. Tests were performed at faults levels of 12 kA peak , 5 kA rms and 2.7 kA rms for 137 V. Measured and simulated results were compared, resulting in a relative error of less than 12%. Two contributions can be highlighted: the new design of the R-SFCL and the inclusion in the convection heat exchange model curves for the heating (during the quench) and cooling (after fault), which allows to predict the recovery under load.

Electrical faults on medium voltage electric power distribution systems can damage transformers. This fact motivated an R&D project in Brazil to study Fault Current Limiters for a utility. In this context, innovative design with a bifilar winding was developed for the present work, aiming to reduce self-inductance and to improve cooling rate. Long length second-generation superconducting tapes were used to build the prototype, which was constructed on a fiber-glass base. The prototype module has been tested at low voltage levels. The nominal operation, fault current limitation and recovery time have been examined for prospective currents of 2700 A and reduction of about 90 % in the current level. Due to fast recovery time and good heat exchange, the proposed topology has potential to be applied in a full-scale prototype.

Resumo -O aumento da demanda de energia elétrica e o crescimento da geração distribuída levam ao aumento da corrente de curto-circuito nas subestações. A maioria das subestações brasileiras, por exemplo, foram projetada décadas atrás, portanto seus equipamentos podem não suportar os novos níveis de corrente de curtocircuito. Para proteger os equipamentos instalados ou evitar altos custos de investimento na sua substituição destes, é possível instalar limitadores de corrente de curto-circuito. Este trabalho apresenta uma avaliação de duas topologias de limitadores através de análises dos aspectos técnicos e operacionais. Protótipos de pequena escala são empregados para entender melhor essas análises. As topologias estudadas são denominadas indutor série chaveado e circuito ressonante. A corrente de curto-circuito teve uma redução para a topologia indutor série chaveado de 69,7% e 72,6% para a topologia ressonante.Abstract -The increase in demand for electric power and the growing of distributed generation led to the increase of the short-circuit current in the substations. Most of these Brazilian substations, for example, were designed decades ago, so their equipment may not support the new short-circuit current levels. To protect the installed equipment or to avoid high investment costs in replacing them, it is possible to install fault current limiters. This work provides technical evaluation of two known topologies of fault current limiters through theoretical analyses of technical and operational aspects. Small-scale prototypes are employed to get a better understanding of those analyses. The studied topologies are called series switched-inductor and resonant circuit. The short-circuit current had a reduction for the switched-inductor topology of 69.7% and 72.6% for the resonant topology.

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