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The increased capacity of multi-level cells (MLC) and triple-level cells (TLC) in emerging non-volatile memory (NVM) technologies comes at the cost of higher cell write energies and lower cell endurance. In this article, we describe MFNW, a Flip-N-Write encoding that effectively reduces the write energy and improves the endurance of MLC NVMs. Two MFNW modes are analyzed: cell Hamming distance mode and energy Hamming distance mode. We derive an approximate model that accurately predicts the average number of cell writes that is proportional to the energy consumption, enabling word length optimization to maximize energy reduction subject to memory space overhead constraints. In comparison to state-of-the-art MLC NVM encodings, our simulation results indicate that MFNW achieves up to 7%--39% saving for 1.56%--50% NVM space overhead. Extra energy saving (up to 19%--47%) can be achieved for the same NVM space overhead using our proposed variations of MFNW, i.e., MFNW2 and MFNW3. For TLC NVMs, we propose TFNW that can achieve up to 53% energy saving in comparison to state-of-the-art TLC NVM encodings. Endurance simulations indicate that MFNW (TFNW) is capable of extending MLC (TLC) NVM life by up to 100% (87%).

This paper describes a low overhead, offline frequent value encoding (FVE) solution to reduce the write energy in multi-level/triplelevel cell (MLC/TLC) non-volatile memories (NVMs). The proposed solution, which does not require any runtime software support, clusters a set of general-purpose applications according to their data frequency profiles and generates a dedicated offline FVE that minimizes write energy for each cluster. Results show that the write energy reduction of evaluation sets-using FVEs generated for training sets-are close (equal) to the best known solution for MLC (TLC) NVM encoding; however, our solution incurs a memory overhead that is 16× (5.7×) less than the best comparable scheme in the literature for MLC (TLC) NVMs.

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on critical path tracing and hence it may result in a reduction in the fault coverage. However, based on experimental results on ISCAS benchmark circuits, the drop in the fault coverage (if any) after relaxation is small for most of the circuits. The technique is faster than the brute-force test relaxation method by several orders of magnitude. 0-7803-7596-3/02/$17.00 02002 IEEE